Electrostatic discharge (ESD) protection circuitry is an essential part of modern integrated circuits. Extremely small delicate device structures are very sensitive to the high voltages which may be generated by contact with the electrostatic charge developed by the human body. During installation of integrated circuits into products, these electrostatic discharges may destroy integrated circuits (ICs) and thus require expensive and tedious repairs on fully manufactured devices which could have been avoided by providing a mechanism for dissipation of the electrostatic discharge to which the IC may be subjected. This problem is particularly acute in complementary metal oxide semiconductor field effect transistor (CMOS) type integrated circuits. In high density CMOS devices, an extremely high voltage may be developed by electrostatic discharge which easily destroys the very thin gate oxides and very short channel devices of the integrated circuit.
To protect against these overvoltage conditions it has been proposed that a silicon controlled rectifier (SCR) structure compatible with CMOS processing be utilized. One such structure is shown in coassigned application Ser. No. 213,499, filed Jun. 27, 1988. Other SCR structures are shown in coassigned U.S. Pat. Nos. 4,896,243 and 4,939,616.
ESD protection for MOS output buffers has typically relied on a parasitic lateral bipolar transistor of the MOS devices. When the voltage reaches the breakdown voltage of the devices, the lateral transistors should turn on and clamp the pad voltage at a sufficiently low voltage to protect the output buffer. The devices typically have a snap-back characteristic during breakdown. The parasitic transistor triggers at a high voltage and snaps-back to a lower voltage to clamp the pad voltage. However, a portion of the MOS device can trigger and snap-back to a lower voltage and conduct all of the current. When this happens, this part can be destroyed before the voltage rises high enough to trigger the rest of the device. This is especially a problem for devices with low resistance substrates, since the substrate is the base of the parasitic lateral transistors and the base is difficult to forward bias if it has a low resistance. Low resistance substrates are desirably used on CMOS circuits to prevent latchup of parasitic SCRs in normal operation, however. This conflicts with the use of SCRs for ESD protection.
Because of the importance of ESD protection, it is desirable to improve and provide alternative ESD protection circuits. Desirable improvements include those which are particularly adaptable for CMOS circuits with low resistance substrates.